Register alias tables are known in computer processors. A register alias table (RAT) may be used to map a logical register, for example as referred to in an operand of a software instruction, to a physical register actually used to carry out the instruction. “Map” as used here means to define a correspondence between. Reading and writing to the RAT for purposes of performing the mapping may be referred to as “renaming” instructions
RATs are increasingly becoming heavily-ported structures. “Ported” refers to how the contents of a RAT are read and written. Each instruction that refers to registers requiring mapping in a RAT may require a plurality of corresponding RAT entries that need to be read/written. For example, computer instructions known as “uops” (“micro-operations”) may have 2 source register fields and 1 destination register field. Therefore, accessing entries in a RAT corresponding to each of these register fields may require 3 read ports and 1 write port: 2 read ports for the 2 source fields, a read port for the destination field, and a write port for the destination field. For a processor that renames 4 uops per cycle, therefore, 12 read ports and 4 write ports may be required.
As structures become more heavily ported, they must typically become larger, consequently incurring a greater penalty in terms of area requirements, access latency and power consumption. This may be seen by considering that, for example, a RAT entry requiring 16 ports as described above needs to have memory cells with areas respectively able to accommodate 16 word lines and 16 bit lines; i.e., area requirements may increase on the order of a power of 2 as ports are added, with corresponding latency effects and increased power consumption. Such disadvantages are, of course, further exacerbated as the number of entries in a RAT increases. The latter may be of particular concern in processors that need to run multiple threads simultaneously, because the RAT needs to store mappings for architectural registers for each thread.